The PIC Architecture

2.8) The PIC Architecture :

The PIC uses a Harvard architecture    , which means that the code and data spaces are completely separated. Most other CPU's use the Vonneuman architecture, where code and data share a common address range. On a PIC code address 0 and data address 0 have nothing to do with each other, and can even address a different number of bits. The addressable element in the PIC data space is a byte (8 bits), the addressable element in the PIC code space is the instruction, which is 12 bits on the 12-bit cores (for instance the 12C509), 14-bit on the 14-bit cores (16x84, 16F628, 16F87x), and 16 bit on the 16-bit cores (18Fxxx).
There are three memory blocks (PIC 16F877) MCU. The program memory, data memory, and EEPROM data memory .

Table (2.1): A comparing of some PICs.

 

Table (2.2): PIC 16F877 pin out description

 

 Legend:
I = input O = output I/O = input/output P = power
— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt trigger input when configured as an external interrupt.
2: This buffer is a Schmitt trigger input when used in serial programming mode.
3: This buffer is a Schmitt trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave Port mode (for interfacing to a microprocessor bus).
4: This buffer is a Schmitt trigger input when configured in RC oscillator mode and a CMOS input otherwise.